HIGH-LEVEL SYNTHESIS UNDER I/O TIMING AND MEMORY CONSTRAINTS

The design of complex Systems-on-Chips implies to take into account communication and timing constraints but also internal memory architecture and mapping for the integration of dedicated hardware accelerator. We present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer in finding a reasonable trade-off between the circuit’s latency and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm