A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems

Abstract. This paper describes a technique for modeling and estimating the power consumption at the system-level for embedded VLIW (Very Long InstructionWord) architectures.The method is based on a hierarchy of dynamic power estimation engines: from the instruction-level down to the gate/transistor-level. Power macro-models have been developed for the main components of the system: theVLIWcore, the register file, the instruc-tion and data caches.Themain goal is to define a system-level simulation framework for the dynamic profiling of the powerbehavior during the software execution,providing also abreak-downof the power contributions due to the single components of the system.The proposed approach has been applied to the Lx family of scalable em-beddedVLIWprocessors, jointlydesignedby STMicroelectronics andHPLabs.Experimental results, carriedout over a set of benchmarks for embedded multimedia applications, have demonstrated an average accuracy of 5% of the instruction-level estimation engine with respect to theRTL engine,with an average speed-up of four orders of magnitude