Full-chip process simulation for silicon DRC

We have developed fast IC process simulation technique based on an empirical resist and etch models to compute the silicon image of designs as large as a full ULSI chip. The simulated silicon image is used to verify the correct electrical operation of the chip and its compliance to semiconductor manufacturing rules. This significantly reduces the manufacturing and development turn-around-time (TAT) by decreasing the number of costly and time-consuming manufacturing test cycles. The basis of these techniques is a fast edge-based optical and process simulator. An edge-movement algorithm is used to compute the displacements of edge fragments in the original design, yielding an approximation to the silicon image. In this paper we will demonstrate the need for Silicon DRC, describe the simulation and image computation algorithms, and illustrate the usefulness of the technique on real circuits