SEU Mitigation Techniques for Microprocessor Control Logic∗

The importance of fault tolerance at the processor archi-tecture level has been made increasingly important due to rapid advancements in the design and usage of high per-formance devices and embedded processors. System level solutions to the challenge of fault tolerance flag errors and utilize penalty cycles to recover through the re-execution of instructions. This motivates the need for a hybrid technique providing fault detection as well as fault masking, with minimal penalty cycles for recovery from detected errors. We propose three architectural schemes to protect the con-trol logic of microprocessors against Single Event Upsets (SEUs). High fault coverage with relatively low hardware overhead is obtained by using both fault detection with re-covery and fault masking. Control signals are classified a