Add to ORKGThe pipelined architecture is one of the most popular ADC architecture. Various linear and nonlinear errors limit the pipelined ADC’s performance. Many calibration algorithms to calibrate this architecture ADC have been reported in literature. In this paper, a new background self-calibration scheme for pipelined ADCs is presented and this calibration scheme can correct both linear and nonlinear errors in the pipelined data path. Simulation shows that with this calibration scheme, the ENOB of a 16-bit pipelined ADC can be improved from 10bits to about 15 bits. 1
Chip makers suffer from the performance degradation of pipelined ADCs, due to the capacitance mismat...
In this paper, we present a digital background calibration technique for pipelined analog-to-digital...
This thesis provides a novel continuous calibration technique for pipelined Analog-to- Digital Conve...
Abstract—This work presents a self-calibration algorithm that corrects the linearity errors of pipel...
This report presents a simulation model design of a 10-bits pipelined ADC with background calibratio...
In this paper, a combined digital foreground self-calibration algorithm is designed to calibrate the...
This thesis presents a novel adaptive self-calibration scheme that can correct linear static errors ...
Continuous digital calibration technique suitable for implementation in a fully monolithic pipeline ...
International audienceA foreground digital calibration technique for pipelined ADC is proposed which...
The linearity of a pipeline analog-to-digital converter (ADC) is mainly limited by capacitor mismatc...
<div><p>Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based ...
The linearity of a high-resolution pipelined analog-to-digital converter (ADC) is mainly limited by ...
This paper presents a new digital technique for back-ground calibration of gain errors in Pipeline A...
An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vi...
Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method r...
Chip makers suffer from the performance degradation of pipelined ADCs, due to the capacitance mismat...
In this paper, we present a digital background calibration technique for pipelined analog-to-digital...
This thesis provides a novel continuous calibration technique for pipelined Analog-to- Digital Conve...
Abstract—This work presents a self-calibration algorithm that corrects the linearity errors of pipel...
This report presents a simulation model design of a 10-bits pipelined ADC with background calibratio...
In this paper, a combined digital foreground self-calibration algorithm is designed to calibrate the...
This thesis presents a novel adaptive self-calibration scheme that can correct linear static errors ...
Continuous digital calibration technique suitable for implementation in a fully monolithic pipeline ...
International audienceA foreground digital calibration technique for pipelined ADC is proposed which...
The linearity of a pipeline analog-to-digital converter (ADC) is mainly limited by capacitor mismatc...
<div><p>Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based ...
The linearity of a high-resolution pipelined analog-to-digital converter (ADC) is mainly limited by ...
This paper presents a new digital technique for back-ground calibration of gain errors in Pipeline A...
An analog-to-digital converter (ADC) is a link between the analog and digital domains and plays a vi...
Measurement and calibration of an analog-to-digital converter (ADC) using a histogram-based method r...
Chip makers suffer from the performance degradation of pipelined ADCs, due to the capacitance mismat...
In this paper, we present a digital background calibration technique for pipelined analog-to-digital...
This thesis provides a novel continuous calibration technique for pipelined Analog-to- Digital Conve...