We address the property checking problem for SoC design verification at the register transfer level (RTL) by integrating techniques from integer programming, constraint programming, and SAT solving. Specialized domain propagation and preprocessing algorithms for individual RTL operations extend a general constraint integer programming framework. Conflict clauses are learned by analyzing infeasible LPs and deductions, and by employing reverse propagation. Experimental results show that our approach outperforms SAT techniques for proving the validity of properties on circuits containing arithmetics
Asynchronous reactive systems form the basis of a wide range of software systems, for instance in th...
In this paper, we study the application of propositional deci-sion procedures in hardware verificati...
Software plays an important role in our daily lives. There is software in our cell phones, in our wo...
The increasing complexity of modern SoC designs makes tasks of SoC formal verification a lot more c...
Satisfiability of complex word-level formulas often arises as a problem in formal verification of ha...
In recent years, formal property checking has become adopted successfully in industry and is used in...
The purpose of this work is the development of a collection of satisfiability based algorithms that ...
This paper provides an overview on recently developed model generation techniques for SAT-based prop...
In this paper we present the Properties Specification Language (PSL) utilization in a system level v...
In this paper a new framework for formal verification is presented. The new framework called EVRM (E...
Steadily increasing design sizes, make the verification a bottleneck in modern design flows of digit...
This dissertation shows that the bounded property verification of hardware Register Transfer Level (...
Recent advances in solving propositional satisfiability problems (SAT) have extended their applicati...
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking e...
This article introduces constraint integer programming (CIP), which is a novel way to combine constr...
Asynchronous reactive systems form the basis of a wide range of software systems, for instance in th...
In this paper, we study the application of propositional deci-sion procedures in hardware verificati...
Software plays an important role in our daily lives. There is software in our cell phones, in our wo...
The increasing complexity of modern SoC designs makes tasks of SoC formal verification a lot more c...
Satisfiability of complex word-level formulas often arises as a problem in formal verification of ha...
In recent years, formal property checking has become adopted successfully in industry and is used in...
The purpose of this work is the development of a collection of satisfiability based algorithms that ...
This paper provides an overview on recently developed model generation techniques for SAT-based prop...
In this paper we present the Properties Specification Language (PSL) utilization in a system level v...
In this paper a new framework for formal verification is presented. The new framework called EVRM (E...
Steadily increasing design sizes, make the verification a bottleneck in modern design flows of digit...
This dissertation shows that the bounded property verification of hardware Register Transfer Level (...
Recent advances in solving propositional satisfiability problems (SAT) have extended their applicati...
We propose a normalization technique for verifying arithmetic circuits in a bounded model checking e...
This article introduces constraint integer programming (CIP), which is a novel way to combine constr...
Asynchronous reactive systems form the basis of a wide range of software systems, for instance in th...
In this paper, we study the application of propositional deci-sion procedures in hardware verificati...
Software plays an important role in our daily lives. There is software in our cell phones, in our wo...