Performance study of the filter data cache on a superscalar processor architecture

The goal of cache design is to exploit data localities; however, the means to this end vary widely among the cache proposals. This paper concentrates on those cache models that split the first level data cache into two independent organizations that are accessed at the same time by the processor. In a previous paper, we introduced the Filter Data Cache as a scheme that maintains the most heavily referenced blocks in a very small cache placed in parallel with a larger classical first level cache. We showed that on a single-issue processor our scheme performs better block management than two other schemes that split the first level data cache according to the criterion of data locality (NTS and SSNS). In this paper, we check the performance of the Filter Data Cache on a state-of-the-art superscalar processor that achieves a better speedup and a higher number of instructions per cycle (IPC). The results show that our scheme performs better than the other compared schemes that split the cache. Keywords—split data cache, data locality, reuse information, performance evaluation, superscalar processors