Architectures for large-capacity CAMs

Content addressable memories (CAMs) have significantly lower capacities than RAMs. Following a summary of large-capacity CAM applications and a brief tutorial look at CAM operation, this paper reviews the sources of this capacity disadvantage: comparator area overhead and difficulty implementing two-dimensional decoding. Past attempts at achieving higher CAM density and capacity are reviewed, and advantages and disadvantages of each are discussed qualitatively. Architectures are divided into the broad classes of serial and fully parallel. The former include bit-serial, Orthogonal-RAM-based, insertion-memory, word-serial, multiport, vector-centered, pattern-addressable m mory, and systolic associative memory. The latter include standard architectures, post-encoding, and pre-classification. A taxon-omy, providing the first structured comparison of existing techniques, is presented. Thereafter, four architectures (two serial and two fully parallel) are quantitatively analyzed, in terms of delay, area, and power, and the cost-performance measures area x delay and power × delay. The fully-parallel architectures, despite their high cost, produce superior cost-performance results