One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and Vdd/Vth optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements. 1
This paper presents a novel gate sizing methodology to mini-mize the leakage power in the presence o...
PhD ThesisThe effect of manufacturing process variations has become a major issue regarding the esti...
Technology scaling has taken circuit performance to unprecedented levels in the deep submicron regim...
Abstract-The growing demand in the multimedia rich applications are motivating the low-power and hig...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
With the advent of deep-submicron technologies, leakage power dissipation is a major concern for sca...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...
With the technology process scaling, leakage power dissipation is becoming a growing number of perce...
Technology scaling improves the energy, performance, and area of the digital circuits. With further ...
SummaryWith the advent of deep-submicron technologies, leakage power dissipation is a major concern ...
The effectiveness of the robust dynamic circuit is degraded much by the increase in leakage current ...
We describe the impact of process variation on leakage power for a 0.18µm CMOS technology. We show t...
While technology scaling has enabled the design of complex information systems, uncertainty in the V...
Driven by the need for faster devices and higher transistor densities, technology trends have pushed...
The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFE...
This paper presents a novel gate sizing methodology to mini-mize the leakage power in the presence o...
PhD ThesisThe effect of manufacturing process variations has become a major issue regarding the esti...
Technology scaling has taken circuit performance to unprecedented levels in the deep submicron regim...
Abstract-The growing demand in the multimedia rich applications are motivating the low-power and hig...
DoctorAggressive technology scaling makes the process variations a significant problem in VLSI desig...
With the advent of deep-submicron technologies, leakage power dissipation is a major concern for sca...
Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for ...
With the technology process scaling, leakage power dissipation is becoming a growing number of perce...
Technology scaling improves the energy, performance, and area of the digital circuits. With further ...
SummaryWith the advent of deep-submicron technologies, leakage power dissipation is a major concern ...
The effectiveness of the robust dynamic circuit is degraded much by the increase in leakage current ...
We describe the impact of process variation on leakage power for a 0.18µm CMOS technology. We show t...
While technology scaling has enabled the design of complex information systems, uncertainty in the V...
Driven by the need for faster devices and higher transistor densities, technology trends have pushed...
The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFE...
This paper presents a novel gate sizing methodology to mini-mize the leakage power in the presence o...
PhD ThesisThe effect of manufacturing process variations has become a major issue regarding the esti...
Technology scaling has taken circuit performance to unprecedented levels in the deep submicron regim...