A Statistical Approach to V&V for Embedded Systems

We outline how a versatile statistical methodology can be used in the verification and validation (V&V) process. This methodology is illustrated on an example of a com-putation time property for a software implementation of a non-linear real-time controller defined as a function of con-troller state variable values. We compare our approach to verification with some alternative statistical techniques used for estimating execution times and other measures of performance. We close with some topics for future work. 1