Direct synthesis of timed asynchronous circuits

This paper presents a new method to synthesize timed asyn-chronous circuits directly from the specification without gener-ating a state graph. The synthesis procedure begins with a de-terministic graph specification with timing constraints. A tim-ing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation of the specification is synthesized by an-alyzing precedence graphs which are constructed by using the timed concurrency and timed causality relations. The major re-sult of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in syn-thesis time, and generates synthesized circuits that have nearly the same area as compared to previous timed circuit methods. In particular, this paper shows that a timed circuit — not con-taining circuit hazards under given timing constraints — can be found by using the relations between signal transitions of the specification. Moreover, the relations can be efficiently found using a heuristic timing analysis algorithm. By allowing sig-nificantly larger designs to be synthesized, this work is a step towards the development of high-level synthesis tools for sys-tem level asynchronous circuits.