In this paper, we apply dynamic voltage scaling (DVS) to the match-ing metric computation (MMC) used within motion estimation (ME) in typical video encoders. Our approach is based on “soft DSP ” con-cepts. We analyze the effect of ME errors (due to DVS) in over-all coding performance. We propose a model for the resulting rate increase (at a given fixed quantization parameter) as a function of input characteristics and input voltage, for given ME algorithm and MMC architecture. This model is validated using simulations. We then compare ME algorithms and MMC architectures, and propose a method for power saving of the ME process that depend on input characteristics and desired coding performance. As an illustration of the potential benefits of...
Abstract: As the usage of personal mobile devices increase, there are many researches for more effic...
© 2015 IEEE. A wide variety of existing and emerging applications in recognition, mining and synthes...
The progress of VLSI technology towards deep sub-micron feature sizes, e.g., sub-100 nanometer techn...
This thesis presents several block matching techniques which are utilized for motion estimation in v...
Power-aware video coding requires a combination of highperformance and flexibility to satisfy percep...
In this paper we study the computation error tolerance properties of motion estimation algorithms. W...
In this paper, we propose power efficient motion estimation (ME) us-ing multiple imprecise sum absol...
Graduation date: 2004This thesis investigates Dynamic Voltage Scaling (DVS) techniques to lower\ud p...
ABSTRACT Presented is an energy-efficient motion estimation architecture using error-tolerance. The ...
Due to the large amount of data transfers it involves, the motion estimation (ME) engine is one of t...
Power consumption has emerged as an important constraint in the design of mobile video encoders. As ...
Power consumption has emerged as an important constraint in the design of mobile video encoders. As ...
In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scal...
This paper investigates the power efficient motion estimation for real time video codecs. The purpos...
Abstract—The objective of dynamic voltage scaling (DVS) is to adapt the frequency and voltage for co...
Abstract: As the usage of personal mobile devices increase, there are many researches for more effic...
© 2015 IEEE. A wide variety of existing and emerging applications in recognition, mining and synthes...
The progress of VLSI technology towards deep sub-micron feature sizes, e.g., sub-100 nanometer techn...
This thesis presents several block matching techniques which are utilized for motion estimation in v...
Power-aware video coding requires a combination of highperformance and flexibility to satisfy percep...
In this paper we study the computation error tolerance properties of motion estimation algorithms. W...
In this paper, we propose power efficient motion estimation (ME) us-ing multiple imprecise sum absol...
Graduation date: 2004This thesis investigates Dynamic Voltage Scaling (DVS) techniques to lower\ud p...
ABSTRACT Presented is an energy-efficient motion estimation architecture using error-tolerance. The ...
Due to the large amount of data transfers it involves, the motion estimation (ME) engine is one of t...
Power consumption has emerged as an important constraint in the design of mobile video encoders. As ...
Power consumption has emerged as an important constraint in the design of mobile video encoders. As ...
In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scal...
This paper investigates the power efficient motion estimation for real time video codecs. The purpos...
Abstract—The objective of dynamic voltage scaling (DVS) is to adapt the frequency and voltage for co...
Abstract: As the usage of personal mobile devices increase, there are many researches for more effic...
© 2015 IEEE. A wide variety of existing and emerging applications in recognition, mining and synthes...
The progress of VLSI technology towards deep sub-micron feature sizes, e.g., sub-100 nanometer techn...