Rank Idle Time Prediction Driven Last-Level Cache

In modern DDRx memory systems, memory write requests can cause significant performance loss by increasing the mem-ory access latency for subsequent read requests targeting the same device. In this paper, we propose a rank idle time prediction driven last-level cache writeback technique. This technique uses a rank idle time predictor to predict long phases of idle rank cycles. The scheduled dirty cache blocks generated from last-level cache are written back during the predicted long idle rank period. This technique allows ser-vicing write request at the point that minimize the delay it caused to the following read requests. Write-induced inter-ference can be significantly reduced by using our technique. We evaluate our technique using cycle-accurate full-system simulator and SPEC CPU2006 benchmarks. The results shows the technique improves performance in an eight-core system with memory-intensive workloads on average by 10.5% and 10.1 % over conventional writeback using two-rank and four-rank DRAM configurations respectively