A Sink-N-Hoist Framework for Leakage Power Reduction

Power leakage constitutes an increasing fraction of the to-tal power consumption in modern semiconductor technolo-gies. Recent research efforts have tried to integrate architec-ture and compiler solutions to employ power-gating mech-anisms to reduce leakage power. This approach is to have compilers perform data-flow analysis and insert instructions at programs to shut down and wake up components when-ever appropriate for power reductions. While this approach has been shown to be effective in early studies, there are concerns for the amount of power-control instructions be-ing added to programs with the increasing amount of com-ponents equipped with power-gating control in a SoC de-sign platform. In this paper, we present a Sink-N-Hoist framework in the compiler solution to generate balanced scheduling of power-gating instructions. Our solution will attempt to merge power-gating instructions as one com-pound instruction. Therefore, it will reduce the amount of power-gating instructions issued. We perform experiments by incorporating our compiler analysis and scheduling poli-cies into SUIF compiler tools and by simulating the energy consumptions on Wattch toolkits. The experimental results demonstrate that our mechanisms are effective in reducing the amount of power-gating instructions while further in re-ducing leakage power compared to previous methods