Pipelined parallel architectures for high throughput MAP detectors

A maximum a posteriori probability (MAP) detector based on a forward only algorithm with high throughput is con-sidered in this paper. MAP gives the optimal performance and, with Turbo decoding, can achieve performance close to the channel capacity limits. Deep pipelined architecture for the forward only method is presented and compared with the other throughput-increasing methods. Simulation re-sults based on the iterative MAP-LDPC (low-density par-ity check) system are shown. Hardware implementation is-sues that exploit the regularities of the structure are also dis-cussed. 1