Add to ORKGAbstract- A number of techniques to reduce cache leakage have so far been proposed. However, it is not clear that 1) what kind of algorithm can be considered and 2) how much they have impact on energy and performance. To answer the questions, this paper classifies cache-leakage reduction techniques and evaluates their energy-performance efficiency. As a result, we have found that an approach employed by the Drowsy cache [1] achieves the best energy-performance efficiency with low complexity. Moreover, we investigate the potential of the approach on multi-thread program executions
Power consumption in computing today has lead the industry towards energy efficient computing. As tr...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Technology projections indicate that static power will become a major concern in future generations ...
A number of techniques to reduce cache leakage have so far been proposed. However, it is not clear t...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Leakage power in cache memories represents a sizable fraction of total power consumption, and many t...
In the design of embedded systems, especially battery-powered systems, it is important to reduce ene...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Cool Chips X : the 10th anniversary of IEEE Symposium on Low-Power and High-Speed Chips : April 18-2...
Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem ...
Leakage energy optimization for caches has been the target of much recent effort. In this work, we f...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
Power consumption in computing today has lead the industry towards energy efficient computing. As tr...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Technology projections indicate that static power will become a major concern in future generations ...
A number of techniques to reduce cache leakage have so far been proposed. However, it is not clear t...
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay...
As the transistor feature sizes and threshold voltages reduce, leakage energy consumption has become...
Leakage power in data cache memories represents a sizable fraction of total power consumption, and m...
Leakage power in cache memories represents a sizable fraction of total power consumption, and many t...
In the design of embedded systems, especially battery-powered systems, it is important to reduce ene...
Abstract—With the reduction in feature size the static power component, such as the leakage power, d...
If current technology scaling trends hold, leakage power dissipation will soon become the dominant s...
Cool Chips X : the 10th anniversary of IEEE Symposium on Low-Power and High-Speed Chips : April 18-2...
Recently, energy dissipation by microprocessors is getting larger, which leads to a serious problem ...
Leakage energy optimization for caches has been the target of much recent effort. In this work, we f...
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Alth...
Power consumption in computing today has lead the industry towards energy efficient computing. As tr...
4th Workshop on Optimizations for DSP and Embedded Systems : March 26, 2006 : Manhattan, New York, N...
Technology projections indicate that static power will become a major concern in future generations ...