MULTI-TAP CONNECTION ARCHITECTURES FOR APPLICATION SPECIFIC INTEGRATED CIRCUITS

In the last decade, the rapid emergence and popular-ity of reusable core-based designs, poses new challenges to the test-dedicated circuitry, specifically IEEE 1149.1 Test Access Port (TAP) standard. The modern cores tend to have a build-in TAP to facilitate both on-chip design for test (DFT) and design for debug (DFD) implementation and reuse. That has triggered development of numerous multi-TAP architectures. Selecting the correct architecture is con-sidered a key point in reduction of testing and debugging ef-forts, decreasing test time, as well as allowing effortless ar-chitectural reuse across different platforms and integrated circuits (ICs). This paper makes an attempt to fill the gap in presenting a thorough analysis of existing multi-tap ar-chitectures yielding the resulting classification, comparison and summary of all the major multi-TAP architectures. Sev-eral modifications to the existing architectures are proposed and analyzed in detail. 1