In this paper, by using calculus of variations, we determine the op-timal shape for a wire under the Elmore delay model. Coupling capacitance has been taken into consideration explicitly by treat-ing it as another source of grounded capacitance. Given two wires in parallel, one has uniform width and the other has non-uniform width whose shape is described by a function f(x). Let T D be the delay through the non-uniform wire. We determine f(x) such that T D is minimized. We also extend our study to the case where a non-uniform wire has two neighboring wires. Our study shows that the optimal shape function satisfies an integral equation. Numer-ical methods are employed to solve the corresponding differential equation and carry out the integra...
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) f...
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routi...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
We propose to use the dominant time constant of a resistor-capacitor #RC# circuit as a measure of th...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
Elmore delay metric is a widely used model to compute signal delays for both analog and digital circ...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
Abstract The optimal wiresizing problem for nets with multiple sources is studied under the distribu...
With the continuous scaling down of very large scale integrated (VLSI) technologies and increased di...
In this brief, we present a simple close-form delay estimate, based on first and second order moment...
Due to technological scaling and high frequency circuits, fast and effective timing algorithm is a d...
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) f...
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routi...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective f...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
We propose to use the dominant time constant of a resistor-capacitor #RC# circuit as a measure of th...
We present ecient, optimal algorithms for tim-ing optimization by discrete wire sizing and buer in-s...
Elmore delay metric is a widely used model to compute signal delays for both analog and digital circ...
As a remarkable development of VLSI technology, a gate switching delay is reduced and a signal delay...
Abstract The optimal wiresizing problem for nets with multiple sources is studied under the distribu...
With the continuous scaling down of very large scale integrated (VLSI) technologies and increased di...
In this brief, we present a simple close-form delay estimate, based on first and second order moment...
Due to technological scaling and high frequency circuits, fast and effective timing algorithm is a d...
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) f...
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routi...
This paper considers simultaneous gate and wire sizing for gen-eral VLSI circuits under the Elmore d...