Hardware Organization and Evaluation of Division Algorithms

Abstract: The hardware organization of the high-radix SRT division is categorized into two classes which we call the arithmetic model and the table model, where quo-tient digits are selected by means of arithmetic operations and a look-up table, respectively. So far the arithmetic model has not been examined in detail, and its effective-ness has not been shown. In this paper, we propose a hardware organization of the arithmetic model which re-sults in a high performance divider. In the proposed or-ganization a carry propagate adder (CPA) determines the delay of the critical path. This paper describes that we can reduce the CPA by one bit by employing other value for than the conventional one, where is a constant of boundary line dividing the overlap region. Comparing the arithmetic model with the table model, in case of 54 bit divider based on radices 4, 8, and 16, speedups of 3%, 5%, and 6 % are obtained with 1%, %, and 19 % larger area costs than those of the table model, respectively. In case of 114 bit divider, speedups of 4%, 8%, and 9 % are obtained with 1%, %, and 11 % larger area costs, re-spectively. We also show that from comparisons between the SRT division and the restoring division, restoring di-vision is effective for dividers of 32 bits or less