A Survey of Testability Measurements at Various Abstraction Levels

Abstract: The new EDA tools such as high level automatic synthesis and design analysis programs require measurement of testability at one or more levels of abstraction. Depending on the application and the level of the input hardware description, we may need to measure testability of a design at the gate, RTL or behavioral level. This paper presents a survey of various testability methods at these levels. In the last section of this paper, we compare these methods for their applications, speed and complexity of algorithms. 1