Design and Evaluation of Network Interfaces for System Area Networks

iAbstract Much of a computer’s communication performance is determined by how well it inter-acts with networks. Such interaction is critical for latency-sensitive applications, such as parallel programs that send frequent, short messages. Fortunately, networks have improved dramatically, especially System Area Networks (SANs). SANs provide sub-microsecond latency, gigabytes per second bandwidth, and very high reliability to 10-100 hosts. Unfortunately, this dramatic improvement in network performance is seldom deliv-ered to applications. A key bottleneck is the host network interface (NI), which connects a network to a host computer. For example, conventional NIs are usually accessed via direct memory access or uncached, memory-mapped device registers, which can incur latencies between ten and hundreds of microseconds. This thesis investigates novel techniques to improve interactions between a processor and a SAN NI. A key principle underlies these techniques: treat NI access as regular, side-effect-free memory access, and not as a disk interface access. The thesis ’ first contribution shows that such treatment opens up at least eight opportunities for improving processor-N