The paper suggests design methods for reconfigurable hierarchical finite state machines (RHFSM), which possess two following important features: 1) they enable the control algorithm to be divided in modules providing direct support for “divide and conquer ” strategy; 2) they can be reconfigured both statically and dynamically. Run-time reconfiguration permits virtual control systems to be constructed, including systems that are more complex than capabilities of available hardware. It is shown that RHFSM can be synthesised from specification in form of hierarchical graph-schemes with the aid of the considered in the paper VHDL templates. The results of experiments show correctness of the proposed methods and their applicability for the desig...
This paper presents a new approach to model and test hierarchical Graphical User Interfaces (GUIs)....
This article presents an approach that helps convert a given C program into a hardware implementatio...
The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dua...
The paper introduces RHS model for combinatorial computations that describes partitioning of the pro...
This portfolio document is intended to present the work carried out in order to meet the requirement...
Presents Meta VHDL (MV) a hardware description language based on VHDL with the addition of primitive...
Abstract—This paper presents a reconfigurable state transition architecture for the Hybrid Fuzzy-Boo...
We present a novel method for the implementation of finite state machines (FSM) using a reconfigurab...
. Hierarchical state machines are finite state machines whose states themselves can be other machine...
This work deals with the description of a design procedure for hierarchical Fault Tolerant Control (...
This paper presents a novel High-Level Synthesis (HLS) and optimization approach targeting FPGA arch...
The paper suggests a novel method for implementing recursive algorithms in hardware. The required su...
Finite State Controllers (FSCs) are an effective way/nto represent sequential plans compactly. By im...
A hierarchical high level synthesis (HHLS) system, such as AMICAL, allows the obtaining of an archit...
Abstract:- This paper suggests a reusable hardware template (HT) for finite state machines (FSM) and...
This paper presents a new approach to model and test hierarchical Graphical User Interfaces (GUIs)....
This article presents an approach that helps convert a given C program into a hardware implementatio...
The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dua...
The paper introduces RHS model for combinatorial computations that describes partitioning of the pro...
This portfolio document is intended to present the work carried out in order to meet the requirement...
Presents Meta VHDL (MV) a hardware description language based on VHDL with the addition of primitive...
Abstract—This paper presents a reconfigurable state transition architecture for the Hybrid Fuzzy-Boo...
We present a novel method for the implementation of finite state machines (FSM) using a reconfigurab...
. Hierarchical state machines are finite state machines whose states themselves can be other machine...
This work deals with the description of a design procedure for hierarchical Fault Tolerant Control (...
This paper presents a novel High-Level Synthesis (HLS) and optimization approach targeting FPGA arch...
The paper suggests a novel method for implementing recursive algorithms in hardware. The required su...
Finite State Controllers (FSCs) are an effective way/nto represent sequential plans compactly. By im...
A hierarchical high level synthesis (HHLS) system, such as AMICAL, allows the obtaining of an archit...
Abstract:- This paper suggests a reusable hardware template (HT) for finite state machines (FSM) and...
This paper presents a new approach to model and test hierarchical Graphical User Interfaces (GUIs)....
This article presents an approach that helps convert a given C program into a hardware implementatio...
The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dua...