Estimation of cache related migration delays for multi-core processors with shared instruction caches

Multi-core architectures, which have multiple processors on a single chip, have been adopted by most chip manu-facturers. In most such architectures, the different cores have private caches and also shared on-chip caches. For real-time systems to exploit multi-core architectures, it is required to obtain both tight and safe estimations of a num-ber of metrics required to validate the system temporal be-haviour in all situations, including the worst-case: tasks worst-case execution times (WCET), preemption delays and migration delays. Estimating such metrics is very challeng-ing because of the possible interferences between cores due to shared hardware resources such as shared caches, mem-ory bus, etc. In this paper, we propose a new method to estimate worst-case cache reload cost due to a task migration be-tween cores. Safe estimations of the so-called Cache-Related Migration Delay (CRMD) are obtained through static code analysis. Experimental results demonstrate the practicality of our approach by comparing predicted worst-case CRMDs with those obtained by a naive approach. To the best of our knowledge, our method is the first one to pro-vide safe upper bounds of cache-related migration delays in multi-core architectures with shared instruction caches.