Scheduling and resource binding for low power

Decisions taken at the earliest steps of the design pro-cess may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algo-rithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the func-tional units (adders, multipliers) by minimizing the transi-tions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget.