An Architecture for Low-Power High-Performance Embedded Computing

Abstract: There is a growing number of systems that require high-performance low-power embedded solutions. Recently the DARPA PERFECT program set forth an efficiency goal of 75 GFLOPS/W to enable embedded computing in unmanned aerial vehicles (UAVs). As a result of analyzing a typical UAV workload, wide-angle motion imaging (WAMI), we are able to specify a new architecture to enable as much computing on board the UAV as possible. This paper presents the proposed heterogeneous architecture, which includes: 1) accelerators to enable extreme energy-efficiency for key kernels; 2) throughput accelerators, such as GPGPUS or SIMD engines, for highly parallel work; 3) near-threshold parallel general purpose processors to facilitate path-divergent paralle