This paper introduces the Pareto front as a useful analysis tool to explore the design space of MOS Current Mode Logic (MCML) circuits. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. As an example of the flexibility of this design automation approach, the results for an optimized fundamental inverter logic gate are presented. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task. Index Terms — Genetic algorithms, MOS current mode logic
This paper proposes a genetic algorithm for designing combinational logic circuits and studies four ...
Abstract:- Several Evolutionary Algorithms (EAs) are applied in the design and optimization of digit...
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCM...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto...
En este documento se alude al problema de dimensionamiento de circuitos MCML (MOS Current Mode Logic...
Abstract: This paper presents a methodology based on Multiobjective Genetic Algorithms (MOGA’s) for ...
This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order t...
This paper is devoted to the synthesis of combinational logic circuits through computacional intelli...
The design of an analogue integrated circuit is a complex and tedious task which requires many compr...
Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interc...
In this paper, the problem at hand consists in the sizing of an Operational Transconductance Amplifi...
The optimal sizing of analog circuits is one of the most complicated processes, because of the numbe...
Abstract1 — This paper presents a new design automation tool based on a modified genetic algorithm k...
This paper presents a methodology based on Multiobjective Genetic Algorithms (MOGA’s) for the design...
This paper proposes a genetic algorithm for designing combinational logic circuits and studies four ...
Abstract:- Several Evolutionary Algorithms (EAs) are applied in the design and optimization of digit...
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCM...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto...
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto...
En este documento se alude al problema de dimensionamiento de circuitos MCML (MOS Current Mode Logic...
Abstract: This paper presents a methodology based on Multiobjective Genetic Algorithms (MOGA’s) for ...
This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order t...
This paper is devoted to the synthesis of combinational logic circuits through computacional intelli...
The design of an analogue integrated circuit is a complex and tedious task which requires many compr...
Multichip Modules (MCMs) is a packaging technology gaining importance, because it reduces the interc...
In this paper, the problem at hand consists in the sizing of an Operational Transconductance Amplifi...
The optimal sizing of analog circuits is one of the most complicated processes, because of the numbe...
Abstract1 — This paper presents a new design automation tool based on a modified genetic algorithm k...
This paper presents a methodology based on Multiobjective Genetic Algorithms (MOGA’s) for the design...
This paper proposes a genetic algorithm for designing combinational logic circuits and studies four ...
Abstract:- Several Evolutionary Algorithms (EAs) are applied in the design and optimization of digit...
In this paper, we address the problem of the optimum design of two-level MOS Current Mode Logic (MCM...