TPTCGen: A Tools for Temporal Partitioning and Tasks Design Exploration for Massive Data Applications in High Performance Reconfigurable Computers

Abstract—In this work we present an experimental Design Space Exploration(DSE) tool for digital integrated systems, targeting reconfigurable Field Programmable Gate Arrays (FP-GAs) devices designs. The tool, called TPTCGen, is integrated to design specification and high level synthesis tools, aiming an efficient FPGA-based computer application mapping. The approach is based on a temporal partitioning method aiming FPGA area improvement for computational intensive applications and performance increasing, parallelism and reuse-core library exploration. This library is composed by a collection of diferrent hardware cores implementation for each task or function. Thus, it is possible to explore different core space/time rate for each new partition implementation and so reach good perfomance and design on the FPGA devices. Experiments have demonstrated the efficiency of this approach in terms of design quality and solution convergence speed. The main tool algorithm, examples and some results are also presented