Caching techniques for multi-processor streaming architectures

In the world of complex SoCs for consumer applica-tions, multiprocessor architectures usually deploy caching techniques to alleviate the cost of data com-munication between processing elements. In this appli-cation domain, the characteristics of streaming appli-cations play a dominant role in the design of the multi-processor architectures. These characteristics not only influence the design at SoC level, but also permeate the design of lower level blocks, such as caches. This paper proposes three novel techniques for data caching in multiprocessor streaming architectures. These techniques exploit the combination of mecha-nisms from the domains of stream caching and cache coherency, optimizing the effectiveness of data caches in a streaming multiprocessor context. Our first implementation targets cache systems in a multiprocessor architecture for high-definition MPEG decoding, where six function-specific processors com-municate through shared embedded SRAM. Simulation results demonstrate the effectiveness of the presented techniques, even though the caches are of very small dimensions, i.e., 0.12 mm2 in 0.12µ technology. 1