Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses

Multimedia applications are often characterized by a large number of data accesses with regular and periodic ac-cess patterns. In these cases, optimized pipelined memory access controllers can be generated improving the pipeline access mode to RAM. We focus on the design and the im-plementation of memory sequencers that can be automati-cally generated from a behavioral synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way.