etching, adhesive A variety of adhesives have been demonstrated for use in thinning and backside processing of III-V substrates.1-4 Each process exhibits certain limitations based on the adhesive’s chemical or thermal resistance. As a result, an adhesive’s property limitation may drive up costs or reduce throughput by necessitating the use of additional protective aids or special tooling. A new product developed by Brewer Science, Inc. (BSI), WaferBOND™5 adhesive, eliminates the need for such aids by directly simplifying the process. WaferBOND™ adhesive exhibits an unusually high resistance to process conditions, which enables the use of strong acids and bases, stripping solvents, and temperatures in excess of 200ºC. Applied with convention...
The work presented in this paper describes adhesive wafer level bonding with structured intermediate...
This paper is focused on a modified process for silicon direct bonding. Thin intermediate sodium sti...
Project (M.S., Electrical and Electronic Engineering) -- California State University, Sacramento, 20...
Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors...
Back thinning after temporary wafer bonding is a key technology for three dimensional (3D) integrati...
Temporary bonding of wafers to a glass carrier has emerged as a viable method for back thinning and ...
Most advanced IC devices including packaging and substrates are requiring smart solution for wafer t...
This paper reviews a high temperature–resistant spin-on adhesive platform and the equipment solution...
Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integr...
Wafer bonding has become well-known and widely used as the process of adhesion of two flat mirror-po...
In this paper a new class of modified silicon direct bonding processes is presented. The new process...
Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer...
3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered...
Bonding of lift off resist (LOR) was performed to realize temporary wafer bonding without residue. B...
Wafer bonding for Compound Semiconductor proc-essing is a new manufacturing technology, which is hig...
The work presented in this paper describes adhesive wafer level bonding with structured intermediate...
This paper is focused on a modified process for silicon direct bonding. Thin intermediate sodium sti...
Project (M.S., Electrical and Electronic Engineering) -- California State University, Sacramento, 20...
Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors...
Back thinning after temporary wafer bonding is a key technology for three dimensional (3D) integrati...
Temporary bonding of wafers to a glass carrier has emerged as a viable method for back thinning and ...
Most advanced IC devices including packaging and substrates are requiring smart solution for wafer t...
This paper reviews a high temperature–resistant spin-on adhesive platform and the equipment solution...
Temporary wafer bonding for thin wafer processing is one of the key technologies of 3D system integr...
Wafer bonding has become well-known and widely used as the process of adhesion of two flat mirror-po...
In this paper a new class of modified silicon direct bonding processes is presented. The new process...
Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer...
3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered...
Bonding of lift off resist (LOR) was performed to realize temporary wafer bonding without residue. B...
Wafer bonding for Compound Semiconductor proc-essing is a new manufacturing technology, which is hig...
The work presented in this paper describes adhesive wafer level bonding with structured intermediate...
This paper is focused on a modified process for silicon direct bonding. Thin intermediate sodium sti...
Project (M.S., Electrical and Electronic Engineering) -- California State University, Sacramento, 20...