Add to ORKGAbstract- A low power and high speed 8/9 CMOS programmable dynamic frequency divider has been designed. It contains a control bit by which can obtain 1/9 and 1/8 input frequency in output. In spite of the variations in size and structure of circuit, the 53 % improvement in power dissipation has been achieved. Power dissipation about 1.6 mw in a 2.78 GHz Frequency Rate, 2.5 volt power supply circuit is verified by HSPISE simulation
Abstract—A low power divide-by-8 injection-locked frequency divider is presented. The frequency divi...
The design of a 32/33 frequency divider, that can operate with input frequency up to 3GHz is discuss...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
A low power and high speed 8/9 CMOS programmable dynamic frequency divider has been designed. It con...
In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic ...
Abstract-Selection of dynamic dividers in CMOS PLLs for GHzs applications allows remarkable reductio...
A low-voltage programmable frequency divider with wide input frequency range is fabricated in standa...
In this paper design and simulation of a 10 GHz, divide by 16…511 programmable frequency divider bas...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
Background: The frequency divider is a critical element in ultra-high-speed applications of communic...
The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presen...
Abstruct- The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider...
The design of a high-speed wide-band high resolution programmable frequency divider is investigated....
To operate a frequency divider with small input clock power, the self-oscillating frequency of the d...
A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops wi...
Abstract—A low power divide-by-8 injection-locked frequency divider is presented. The frequency divi...
The design of a 32/33 frequency divider, that can operate with input frequency up to 3GHz is discuss...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
A low power and high speed 8/9 CMOS programmable dynamic frequency divider has been designed. It con...
In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic ...
Abstract-Selection of dynamic dividers in CMOS PLLs for GHzs applications allows remarkable reductio...
A low-voltage programmable frequency divider with wide input frequency range is fabricated in standa...
In this paper design and simulation of a 10 GHz, divide by 16…511 programmable frequency divider bas...
A divide-by-four circuit divides frequencies from 31GHz to 41GHz at input signal amplitudes ≤0.5Vpp....
Background: The frequency divider is a critical element in ultra-high-speed applications of communic...
The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presen...
Abstruct- The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider...
The design of a high-speed wide-band high resolution programmable frequency divider is investigated....
To operate a frequency divider with small input clock power, the self-oscillating frequency of the d...
A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops wi...
Abstract—A low power divide-by-8 injection-locked frequency divider is presented. The frequency divi...
The design of a 32/33 frequency divider, that can operate with input frequency up to 3GHz is discuss...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...