Advanced VHDL Constructs And Methodologies For Design Verification

This paper describes, with examples, the use of advanced VHDL constructs that greatly enhance modeling efficiency. The constructs illustrated in this paper include the use of dynamic memory allocation techniques using linearly-searched linked lists for modeling memory elements, use of record data-types for data-bundling in procedure calls, use of shared variables to enhance simulation speed, use of VHDL configurations in a hierarchical test-bench for random stimuli, and embedding timing information within configurations. Also discussed is the use of foreign language interfaces for modeling behavior. All the constructs described are illustrated with real-life examples that were used within VLSI and have greatly enhanced modeling efficiency, portability, and simulation speed among many other advantages. Modeling efficiency, ease of use and reuse for simulation and testing are becoming increasingly important as chip sizes continue to increase beyond one million gates. At VLSI Technology, Tempe, AZ, VHDL has been used extensively as the test/verification language for projects. Many features of VHDL have been utilized for maximum simulation flexibility, usability, and productivity. This paper describes a few techniques that employ advanced VHD