Abstract:In this paper we propose a novel concepts of self-reconfigurable finite state machines in which a delta transition is used for reconfiguration initialization and others reconfiguration sequences are exterior events, a new model of VLSI implementation to describe a certain number of state machines implemented in hardware that may be reconfigured during operation. Hardware is called self-reconfigurable finite state machine with reduced reconfiguration sequences if a delta transition is initialized by the Finite machine itself and some others reconfiguration sequences to update output function or transition function are initiated from exterior event. We propose an efficient concept to reduce the reconfiguration sequences which reduces...
This portfolio document is intended to present the work carried out in order to meet the requirement...
Practically, any digital system includes sequential blocks represented using a model of finite state...
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state ...
We present a novel method for the implementation of finite state machines (FSM) using a reconfigurab...
Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into...
Abstract:- This paper suggests a reusable hardware template (HT) for finite state machines (FSM) and...
New algorithms of coding the internal states of finite-state machine (FSM) have been (were) proposed...
The purpose of this thesis is to continue development of a single state rep-resentation for use in a...
Clock-gating techniques are very effective in the reduction of the switching activity in sequential ...
This paper presents a finite state machine (FSM) re-engineering method that enhances the FSM synthes...
The paper describes an algorithm for state encoding finite state machines targeting low-power realiz...
A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead ...
The mathematical model for designing a complex digital system is a finite state machine (FSM). Appli...
This letter proposes a new model of state machine called Finite Virtual State Machine (FVSM). A memo...
This paper presents a state assignment technique to reduce dynamic power consumption in finite state...
This portfolio document is intended to present the work carried out in order to meet the requirement...
Practically, any digital system includes sequential blocks represented using a model of finite state...
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state ...
We present a novel method for the implementation of finite state machines (FSM) using a reconfigurab...
Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into...
Abstract:- This paper suggests a reusable hardware template (HT) for finite state machines (FSM) and...
New algorithms of coding the internal states of finite-state machine (FSM) have been (were) proposed...
The purpose of this thesis is to continue development of a single state rep-resentation for use in a...
Clock-gating techniques are very effective in the reduction of the switching activity in sequential ...
This paper presents a finite state machine (FSM) re-engineering method that enhances the FSM synthes...
The paper describes an algorithm for state encoding finite state machines targeting low-power realiz...
A method of a self-checking synchronous Finite State Machine (FSM) network design with low overhead ...
The mathematical model for designing a complex digital system is a finite state machine (FSM). Appli...
This letter proposes a new model of state machine called Finite Virtual State Machine (FVSM). A memo...
This paper presents a state assignment technique to reduce dynamic power consumption in finite state...
This portfolio document is intended to present the work carried out in order to meet the requirement...
Practically, any digital system includes sequential blocks represented using a model of finite state...
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state ...