Defining Elastic Circuits with Negative Delays

An elastic circuit can take an arbitrarily long time to compute its results and it can wait arbitrarily long for cooperating circuits to pro-duce its inputs and to consume its outputs. For example, the streams X = 1001 · · · and Y = 0110 · · · could be an observed input/output behavior of an elastic inverter. The transfer of data on the input channel occurs at cycles 1,3,4,7,...; the absence of transfer is shown as the bubble symbol . When we ignore the bubbles, we see a behavior of an ordinary inverter: X ′ = 1001 · · · and Y ′ = 0110 · · ·. Elastic circuits promise novel methods for microarchitectural design that can exploit variable latencies, while still employing standard syn-chronous design tools and methods [1]. The Intel project SELF (Synchronous Elastic Flow) [3, 2] demonstrates the industry interest. In SELF, every elastic circuit E is associated with an ordinary (non-elastic) system S in the “bubble removal ” sense indicated in the inverter example. For each wire X of S, there is a channel 〈DX, VX, SX 〉 in E consisting of the dat