Towards Automatic Translation to Temporally Predictable Code∗

Contemporary Microprocessors are highly optimised to-wards average case performance using caches and branch prediction. While these features provide considerable speedups they come at the price of predictability. How-ever, for real-time applications with timing precision re-quirements in an order of magnitude close the CPU’s clock frequency, tight prediction of WCETs (worst case execu-tion times) is indispensable. We are proposing a concep-tual model and an assembly transformation strategy to turn code with nested conditional control structures into code with a flat flow of control. This so-called single-path code facilitates the prediction of timing behaviour, ideally caus-ing only an negligible overall slowdown. To overcome the burden of writing a full fledged compiler, we are designing our transformation to be applied post-pass, with full sup-port for any optimisations conducted during the preceding compilation stage.