Two Fault Tolerance Design Approaches for Hybrid CMOS/Nanodevice Digital Memories

Targeting on the future fault-prone hybrid CMOS/nanodevice digital memories, this paper presents two fault tolerance design approaches that integrally address the tolerance for defects and transient faults. The first approach is straightforward and easy to implement but suffers from a rapid drop of achievable storage capacity as defect densities and/or transient fault rates increase, while the second approach can achieve much higher storage capacity under high defect densities and/or transient fault rates at the cost of higher implementation complexity and longer memory access latency. With the use of BCH codes as ECC, we carried out simulations to demonstrate the effectiveness of the presented approaches under a wide range of defect densities and transient fault rates, while taking into account of the fault tolerance storage overhead in CMOS domain.