Leveraging Boundary Scan resources for comprehensive cluster testing

Board level Boundary Scan testing as defined in IEEE-1149.1 is well established in the electronics industry. To achieve the best possible test coverage and testability for a specific design, a thorough DfT1 Analysis is required though. DfT for Boundary Scan does not just include routing the scan chain and taking care of compliance pins on Boundary Scan devices. It also concerns non-Boundary Scan circuitry such as logic or memory clusters. Modern memory devices, especially synchronous memories, become more complex and faster with each generation. This paper suggests ways to ensure that those memory clusters will still be testable via Boundary Scan. Also, alternatives to memory cluster tests will be discussed, such as BIST2 and test resources embedded in the memory device. 1