A Novel Design of a Network on Chip Input Buffer Using GALS Technique to Reduce Power Consumption

Abstract — Power consumption can be reduced in clock of large VLSI by adapting Globally Asynchronous Locally Synchronous design style (GALS). This paper, reviewed a design methodology for a globally asynchronous router including locally-synchronous and asynchronous modules and proposed a novel design for Input Buffer of the mentioned router. This buffer, have used special Latches and Single Rail coding with lower power consumption and fewer numbers of transistors and transmission gates comparing to previous designs with PCFBs ( you should put full name and abbreviation) that use Dual Rail coding with very high power consumption and a large number of transistors. The modules are equipped with Asynchronous to/from Synchronous interfaces. For obtaining Fault Coverage, Stuck-at fault has been injected to the circuit. The results show an average power saving of about 73.8 % and Fault coverage of 53%. The designed input buffer has been implemented with VHDL code and simulated in Model Sim Simulator