This paper provides an authoritative knowledge of through-router packet delays and therefore a better understanding of data network performance. Thanks to a unique experimental setup, we capture all packets crossing a router for 13 hours and present detailed statis-tics of their delays. These measurements allow us to build the fol-lowing physical model for router performance: each packet expe-riences a minimum router processing time before entering a fluid output queue. Although simple, this model reproduces the router behaviour with excellent accuracy and avoids two common pitfalls. First we show that in-router packet processing time accounts for a significant portion of the overall packet delay and should not be neglected. Second we point...
We measure and analyze the single-hop packet delay through operational routers in a backbone IP netw...
Discussions of how to measure the performance of computer networks for various applications have bee...
Delays in routers are an important component of end-to-end delay and therefore have a significant im...
The main goals of the paper are towards an understanding of the delay process in best-effort Interne...
The main goals of the paper are towards an understanding of the delay process in best-effort Interne...
The main goals of the tutorial are towards an understanding of the delay process in best-effort In...
The main goals of the tutorial are towards an understanding of the delay process in best-effort Inte...
The main goals of this thesis are towards an understanding of the delay process in best-effort Inter...
Through the study of network characteristics it is possible to predict the overall behavior of netwo...
Abstract — Network processor systems provide the performance of ASICs combined with the programmabil...
In this paper, we perform a detailed analysis of point-to-point packet delay in an operational tier-...
Abstract—Utilizing a highly precise network measurement device, we investigate router’s inherent var...
Packets in the Internet can experience large queueing delays during busy periods. Backbone routers a...
Abstract. Current router models [2, 3, 5, 6] assume that clock cycle time depends solely on router l...
The problem of characterizing the relationship between packet size and network delay has received li...
We measure and analyze the single-hop packet delay through operational routers in a backbone IP netw...
Discussions of how to measure the performance of computer networks for various applications have bee...
Delays in routers are an important component of end-to-end delay and therefore have a significant im...
The main goals of the paper are towards an understanding of the delay process in best-effort Interne...
The main goals of the paper are towards an understanding of the delay process in best-effort Interne...
The main goals of the tutorial are towards an understanding of the delay process in best-effort In...
The main goals of the tutorial are towards an understanding of the delay process in best-effort Inte...
The main goals of this thesis are towards an understanding of the delay process in best-effort Inter...
Through the study of network characteristics it is possible to predict the overall behavior of netwo...
Abstract — Network processor systems provide the performance of ASICs combined with the programmabil...
In this paper, we perform a detailed analysis of point-to-point packet delay in an operational tier-...
Abstract—Utilizing a highly precise network measurement device, we investigate router’s inherent var...
Packets in the Internet can experience large queueing delays during busy periods. Backbone routers a...
Abstract. Current router models [2, 3, 5, 6] assume that clock cycle time depends solely on router l...
The problem of characterizing the relationship between packet size and network delay has received li...
We measure and analyze the single-hop packet delay through operational routers in a backbone IP netw...
Discussions of how to measure the performance of computer networks for various applications have bee...
Delays in routers are an important component of end-to-end delay and therefore have a significant im...