Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance

Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As archi-tectural trends point towards multi-threaded multi-core de-signs, there is substantial interest in adapting such parallel hardware resources for transient fault tolerance. This paper proposes a software-based multi-core alternative for tran-sient fault tolerance using process-level redundancy (PLR). PLR creates a set of redundant processes per application process and systematically compares the processes to guar-antee correct execution. Redundancy at the process level allows the operating system to freely schedule the processes across all available hardware resources. PLR’s software-centric approach to transient fault tolerance shifts the fo-cus from ensuring correct hardware execution to ensuring correct software execution. As a result, PLR ignores many benign faults that do not propagate to affect program cor-rectness. A real PLR prototype for running single-threaded applications is presented and evaluated for fault coverage and performance. On a 4-way SMP machine, PLR provides improved performance over existing software transient fault tolerance techniques with 16.9 % overhead for fault detec-tion on a set of optimized SPEC2000 binaries.