Embedded-Software Refinement

on chip complexity. For example, the evolution from 0.5-to 0.18-micron technology has freed 88 % of chip space.1 This trend continues to follow Moore’s law with 130- and 90-nm technologies. It is now possible to manufacture chips with 100 million transistors—theoretically enough to fit the logic of more than 1,000 32-bit reduced-instruc-tion set computing (RISC) processors on a single die. Leveraging these capabilities is a major challenge, which has led to the adoption of SoC design. Complexity, com-bined with the narrowing of the time-to-market window, has motivated SoC designers to reuse IP blocks and build designs around platforms.2 Unlike ASICs, in which all desired functionality is hardwired, platforms contain programmable devices (for example, processors), and some specific function