2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits

Recent advances in compact, practical adiabatic comput-ing circuits which demonstrate signicant energy savings have renewed interest in using such techniques in low-power systems. Several recently introduced circuits for adiabatic computing make use of diodes in a way which reduces switching energy from O(CV dd 2) in the non-adiabatic (ie: standard CMOS) case, to O(CV ddV t). These circuits provide an energy savings of at most one order of V dd=V t. This paper introduces a new class of adiabatic computing circuits which oer several advan-tages over existing approaches, the primary one being that, because no diodes are used, switching energy can be reduced to an energy oor of O(CV t 2). These sec-ond order adiabatic computing circuits provide an ener-gy savings of as much as O(V dd=V t 2) over conventional CMOS. Additional advantages of the proposed circuits include the fact that, in comparison to most compact adiabatic circuits which have oating output levels over the entire data valid time, these new circuits have non-oating output levels over most of the data valid time. This is important for restoring logic levels and minimiz-ing problems with crosstalk. The proposed circuits have been simulated and demonstrate adiabatic power savings compared to standard CMOS circuits over an operating frequency range from 1MHz to 100MHz of as much as a factor of 3. One circuit topology has been fabricated and tested and operates properly at up to 100MHz, the maxi-mum speed which could be tested. Power measurements on the functioning circuit are in progress and prelimi-nary results demonstrate adiabatic power-vs-frequency behavior. These second order adiabatic computing cir-cuits provide an attractive alternative to achieve adia-batic power savings without suering from many of the limitations of alternative approaches and without cost-ing much more either in terms of complexity or size