Compiler-Assisted Preferred Caching for Embedded Systems with STT-RAM based Hybrid Cache

As technology scales down, energy consumption is becoming a big problem for traditional SRAM-based cache hierarchies. The emerging Spin-Torque Transfer RAM (STT-RAM) is a promis-ing replacement for large on-chip cache due to its ultra low leak-age power and high storage density. However, write operations on STT-RAM suffer from considerably higher energy consump-tion and longer latency than SRAM. Hybrid cache consisting of both SRAM and STT-RAM has been proposed recently for both performance and energy efficiency. Most management strategies for hybrid caches employ migration-based techniques to dynami-cally move write-intensive data from STT-RAM to SRAM. These techniques lead to extra overheads. In this paper, we propose a compiler-assisted approach, preferred caching, to significantly re-duce the migration overhead by giving migration-intensive memory blocks the preference for the SRAM part of the hybrid cache. Fur-thermore, a data assignment technique is proposed to improve the efficiency of preferred caching. The reduction of migration over-head can in turn improve the performance and energy efficiency of STT-RAM based hybrid cache. The experimental results show that, with the proposed techniques, on average, the number of migrations is reduced by 21.3%, the total latency is reduced by 8.0 % and the total dynamic energy is reduced by 10.8%