Gate Sizing for Constrained delay/power/area optimization

Abstract—Gate sizing has a significant impact on the de-lay, power dissipation, and area of the final circuit. It con-sists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is op-timized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a cir-cuit under some user-defined delay constraints, or to obtain the fastest circuit within a given power budget. Although this technology-dependent optimization has been investi-gated for years, the proposed approaches sometimes rely on assumptions, cost models, or algorithms that make them unrealistic or impossible to apply on real-life large circuits. We discusse here a gate sizing algorithm (GS), and show how it is used to achieve constrained optimization. It can be applied on large circuits within a reasonable CPU time, e.g., minimizing the power of a 10000 nodes circuit under some delay constraint in 2 hours. Keywords—Gate sizing, discrete constrained optimization, delay/power/area tradeoff I