Low Voltage Memories for Power-Aware Systems

This paper describes low-voltage RAM designs for stand-alone and embedded memories in terms of signal-to-noise-ratio designs of RAM cells and subthreshold-current reduction. First, structures and areas of current DRAM and SRAM cells are discussed. Next, low-voltage peripheral circuits that have been proposed so far are reviewed with focus on subthreshold-current reduction, speed variation, on-chip voltage conversion, and testing. Finally, based on the above discussion, a perspective is given with emphasis on needs for high-speed simple non-volatile RAMs, new devices/circuits for reducing active-mode leakage currents, and memory-rich SOC architectures. Keywords subthreshold current, DRAM and SRAM cells, gain cells, peripheral circuits, gate-source/substrate-source back-biasing, multi-VT, on-chip voltage converters, testing, non-volatile RAMs, memory-rich architectures