CLOCK DISTRIBUTION NETWORKS WITH GRADUAL SIGNAL TRANSITION TIME RELAXATION FOR REDUCED POWER CONSUMPTION

Clock distribution network consumes a significant portion of the total chip power since the clock signal has the highest activity factor and drives the largest capacitive load in a synchronous integrated circuit. A new methodology is proposed in this paper for buffer insertion and sizing in an H-tree clock distribution network. The objective of the algorithm is to minimize the total power consumption while satisfying the maxi-mum acceptable clock transition time constraints at the leaves of the clock distribution network for maintaining high performance. The new methodology employs nonuniform buffer insertion and progressive relaxation of the transition time requirements from the leaves to the root of the clock distribution network. The proposed algorithm provides up to 30 % savings in the total power consumption without sacrificing clock skew as compared to a standard algorithm with uniform buffer insertion aimed at maintaining uniform transition time constraints at all the nodes of a clock tree in a 180 nm CMOS technology