Low-Power Configurable Logic Block (CLB) Design for FPGAs

Logic Blocks (CLB), with a routing architecture that connects these blocks together (Figure 1). An island-style FPGA structure is investigated and the CLB is explored in order to reduce its power consumption. Approximately 16 percent of the FPGA power is consumed by the CLBs alone. As technology nodes scale down, the leakage power is going to increase in these logic blocks. Also, its effects on the total power should not be ignored for FPGA cores that can be embedded within an ASIC architecture. This work explores methods for reducing the power consumption of each CLB and comparing it to a standard CLB. I. CLB Power Reduction Methods The components of the CLB are latches (in place of SRAM cells), muxes, and flipflop. The methods considered are multithreshold CMOS, clock gating, and variable gate length transistors. Previous work on creating a low energy FPGA explored many architectures and circui