Digital Systems Architectures Based on On-line Checker

In this paper, a methodology for generating VHDL de-scriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line check-ers of communication protocols, counters, decoders, reg-isters, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the de-sign of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented. 1