W.F.: An inter-core communication enabled multi-core simulator based on simplescalar

In the recent years, multi-core processors prove their ex-tensive use in the area of System-on-Chip (SoC) on a single chip. This paper proposes a methodology and implements a multi-core simulator. The multi-core simulator is based on SimpleScalar integrated with SystemC framework, which deals with communication and synchronization among dif-ferent processing modules. A shared memory scheme is in-troduced for inter-core communication with a set of shared memory access instructions and communication methods. A synchronization mechanism, which only switches the simu-lation component when communication occurs, is proposed for efficiency. Experiments prove that our simulator can correctly simulate the behavior of a multi-core system and demonstrate a high performance on Linux PC platforms.