Predictable Reactive Processors for Next Generation Computing: A Proposal

Researchers at Auckland University and Kiel University have been working on a family of processors they term as reactive processors [20]. Reactive architectures are specialized embedded processors that directly interact with the environment through a specialized instruction set architecture (ISA). The hallmark of reactive processing is timing predictability and efficient resource usage, using the synchronous model of execution as exemplified by the Esterel programming language. The initial idea was proposed by Salcic and Roop of Auckland University in 2002 and was subsequently explored and extended by the research team of von Hanxleden et al. at Kiel University. Predictable execution of embedded systems using processors that guarantee timing has also gained momentum through the concept of Precision timed or PRET machines recently advocated by Edwards and Lee at DAC 2007 [8]. While architectures since the early 80s went for average case performance increase as the main metric of success, Edwards and Lee argue that “it is time for a new era of processors whose temporal behaviour is as easily controlled as their logical function”. There is good evidence that the reactive processing approach has much to offer here, and the goal of the work proposed here is to investigate how the diverse approaches taken at Auckland and Kiel can be combined and extended. Specifically, we would like (1) to investigate alternative ISAs that offer predictable timing, starting from high-level programs given in Esterel and possibly other languages, such as Java, (2) to investigate suitable models for distributed reactive processing, and (3) to build the foundations for a family of next-generation reactive processors that guarantee predictable execution